ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
B Implementation restrictions
ST40RA166
B.2.5 Master abort
When operating as a bus master, the PCI module is not guaranteed to have the value 0xFFFF FFFF
following a master abort of a read cycle. The master abort may be detected using either the PCI
module status and interrupt information supplied by the module.
B.3 EMI/EMPI
B.3.1 EMPI burst mode operation: ST40RA166 MPX target
MPX operations using the ST40RA166 as the target which lead to burst requests to memory (Read
ahead, 8-, 16- and 32-byte read operations) have limited support.
MPX operations from the ST40RA166 as an initiator includes full support for all transfer sizes.
B.3.2 SDRAM initialization during boot from flash
During the SDRAM initialization sequence only internal EMI registers are accessible, it is therefore
necessary to ensure the program required to execute the initialization sequence is placed in an
alternate memory location such as the LMI or preloaded into the cache.
B.3.3 MPX boot
BootFromMPX is not supported on this part.
B.4 Mailbox
B.4.1 Test and set functionality
This is not supported.
B.5 Power down
B.5.1 Module power-down sequencing
Whilst powering down using the associated registers for the ST40RA166 module, in general,
software is responsible for ensuring the module is in a safe state before requesting module
shutdown. For details refer to the appropriate documentation.
B.5.2 Accesses to modules in power-down state
Once a module is in power-down state, attempts to access that module may lead the system to
hang.
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