ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
Revision history
Revision history
Version D
Cover
Version
3 ST40 systems using the ST40RA166
4 ST40RA166 system organization
Section 4.6: EMI address pin mapping on page 18
5 Electrical specifications
Section 6.2: Rise and fall times on page 44
Version C
Comments
Title changed
Old Figure 1 replaces cover diagram
Section removed
Definition of address lines on EMI interface in 8-, 16- and 32-
bit data width
Rise and fall times for the memory interfaces
Name change from ST40STB1 to ST40RA166
New sections
5.2 System identifiers
5.6.8 PLL programming formulas
5.6.9 PLL stabilization times
6.1.1 Fmax clock domains
6.5 DDR bus termination (SSTL_2)
B1.3 UBC power down
B2.2 Type 2 configuration accesses
B8 LMI
B9 GPDMA
B10 RTC clock
New tables
Table 31 Power dissipation
New figures
Figure 2 Pocket multimedia device
Figure 8 Pads characteristics for SL, P8, C2A and C2B pad
types
Figure 9 Pad characteristics for C4 and E4 pad types
Figure 13 SSTL_2 bus termination
Sections revised
Cover: bus interface figures for LMI and EMI changed
3 ST40 systems using the ST40RA166: rewording
6 Electrical specifications: AC/DC characterisation figures
changed
B2.3 Software visible changes between ST40RA166HC7 and
ST40RA166H8D: used to be MBAR register definition
B3.1 EMPI burst mode operaton: ST40RA166 MPX target:
clarifying sentence added at end
B9.2 2D transfers: point 3 explained more fully
86/88
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