ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
B Implementation restrictions
ST40RA166
B.7 Interconnect
B.7.1 Memory bridge functionality
Ensure there is no traffic passing though the memory bridge when changing frequency.
Semisynchronous modes of operation are not supported.
B.7.2 Clock selection
The alternate CLOCKGENB clock is not supported for the LMI.
B.7.3 Pad drive control
Programmable drive strength control is not supported for DDR operation.
B.8 GPDMA
B.8.1 Linked list support
Decrementing transfers are not supported as part of link list transfer sequences
B.8.2 2-D transfers
2-D transfers fail if the following conditions are met.
1 Source or destination length is greater than 64 bytes.
2 Real transfer unit is less then 32 bytes.
3 The expression length = n * 64 + tu is true, where:
length is either SLENGTH or DLENGTH,
tu the real transfer unit of the first access of the second line,
n > 0.
B.8.3 Protocol signals
DACK and DRACK protocol signals have limited support.
B.9
RTC clock
The feedback circuit for the LPCLK and LPOSC clock generation to the TC fails if the main core supply
is removed. In applications where this may occur, an LPCLK should be generated externally.
85/88
Share Link: 
