ST6285B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6285B' PDF : 78 Pages View PDF
ST62T85B/E85B
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h — Read/Write
7
0
PS2 PS1 PS0 D4
-
- CC1 CC0
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: EBh — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 16. Prescaler Division Ratio Selection
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
PS2 PS1 PS0 ARPSC Division Ratio
AR Reload/Capture Register. The ARRC re-
0
0
0
1
0
0
1
2
t(s) 0
1
0
4
0
1
1
8
uc 1
0
0
16
d 1
0
1
32
ro 1
1
0
64
P 1
1
1
128
te Bit 4 = D4: Reserved. Must be kept reset.
le Bit 3-2. Reserved. Must be cleared to zero
o Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
bs These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
O the clock sources is explained in the following Table
- 17:
t(s) Table 17. Clock Source Selection.
c CC1
CC0
du 0
0
ro 0
1
Obsolete P Others
Clock Source
Fint
Fint Divided by 3
Reserved
load/capture register is used to hold the auto-re-
load value which is automatically loaded into the
counter when overflow occurs.
AR Reload/Capture (ARRC)
Address: E9h — Read/Write
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: EAh — Read/Write
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7-0 = D7-D0: Compare Data Bits. These are
the Compare register data bits.
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