ST6285B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6285B' PDF : 78 Pages View PDF
ST62T85B/E85B
4.4 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn- 4.4.1 PORTS INTERFACING
chronous serial communication which, combined
with an appropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 38,400 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
Operating in Half-Duplex mode only, the UART defined as input mode (with or without pull-up)
uses 11-bit characters comprising 1 start bit, 9 data while the I/O line common with TXD line must be
bits and 1 Stop bit. Parity is supported by software defined as output mode (Push-pull or open drain).
only for transmit and for checking the received par- The transmitted data is inverted and can therefore
ity bit (bit 9). Transmitted data is sent directly, while use a single transistor buffering stage. Defined as
received data is buffered allowing further data input, the RXD line can be read at any time as an
characters to be received while the data is being I/O line during the UART operation. The TXD pin
read out of the receive buffer register. Data trans- follows I/O port registers value when UARTOE bit
mit has priority over data being received.
is cleared, which means when no serial transmis-
The UART is supplied with an MCU internal clock
) that is also available in WAIT mode of the processor.
ct(s Figure 23. UART Block Diagram
sion is in progress. As a consequence, a perma-
nent high level has to be written onto the I/O port in
order to achieve a proper stop condition on the
TXD line when no transmission is active.
) - Obsolete Produ WRITE
roduct(s READ
START
DETECTOR
UARTOE
TXD
DIN DATA SHIFT DOUT
REGISTER
DR
D8 D7 D6 D5 D4 D3 D2 D1 D0
RECEIVE BUFFER
REGISTER
1
MUX
0
RXD1
TXD1
bsolete PRX and TX
O INTERRUPTS
CONTROL REGISTER D9
BAUD RATE
fINT
BAUD RATE x 8
PROGRAMMABLE
DIVIDER
VR02009
47/78
47
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