ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
DMT Symbol Timing Unit (DSTU)
The DSTU interfaces with various modules, like
DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS,
Monitor and Transceiver Controller. It consists of a
real time and a scheduler modules.
The real time unit generates a timebase for the
DMT symbols (sample counter), superframes
(symbol counter) and hyper-frames (sync
counter). The timebases can be modified by
various control features. They are continuously
fine-tuned by the DPLL module.
The DSTU schedulers execute a program,
controlled by program opcodes and a set of
variables, the most important of which are real
time counters.
The transmit and receive sequencers are
completely independent and run different
programs. An independent set of variables is
assigned to each of them. The sequencer
programs can be updated in real time.
ST70235A interfaces
Overview
See Figure 9.
Processor Interface (ATC)
The ST70235A is controlled and configured by an
external processor across the processor interface.
All programmable coefficients and parameters are
loaded through this path.
Data and addresses are multiplexed
ST70235A works in 16 bits data access, so
address bit 0 is not used. Address bit 1 is not
multiplexed with data. It has its own pin : BE1.
Byte access are not supported. Access cycle read
or write are always in 16 bits data wide, ie bit
address A0 is always zero value.
The interrupt request pin to the processor is INTB,
and is an Open Drain output.
The ST70235A supports both little and big endian.
The default feature is big endian.
Figure 9 : ST70235A Interfaces
AFE INTERFACE TO ADSL LINE (ST70134)
RESET
JTAG
CLOCK
ST70235A
PROCESSOR
INTERFACE
(ATC)
DIGITAL INTERFACE UTOPIA
Generic Interface
This interface is suitable for a number of
processors using a multiplexed Address/data bus.
In this case, synchronization of the input signals
with PCLK pin is not necessary.
Figure 10 : Generic Processor Interface Write Timing Cycle
MClk
ALE
CSB
Address/DATA
Talew
Tale2cs
Tavs Tavh
WRB 1
RDYB
1: RDB = WR_RDB is high.
Tcs2wr
Twr2Mclk
Twr2d
Twr2rdy
Tcsre
Trdy2cs
Trdy2wr
Tmclk
13/28
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