ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Figure 11 : Generic Processor Interface Read Timing Cycle
MClk
ALE
CSB
Address/DATA
RDB 1
RDYB
1: WRB = BE1 is high.
Tale2Z
Talew
Tale2cs
Tavs
Tavh
Tcs2rd
Trd2Mclk
Trd2rdy
Tcsre
Twrw
Trdy2cs
Tdvs
Tdvh
Trdy2rd
Tm clk
Generic processor interface Cycle Timing
All AC characteristics are indicated for a 100pF capacitive load.Cycle timing for generic interface.
Table 2 : Cycle timing
Symbol
Tcsre
Talew
Tavs
Tavh
Tale2cs
Tale2Z
Tcs2wr
Tcs2rd
Twr2d
Twr2rdy
Trd2rdy
Trdy2wr
Trdy2rd
Tdvs
Tdvh
Trdy2cs
Tmclk
Twr2Mclk
Trd2Mclk
Parameters
Access Time
Ale pulse width
Address valid setup time
Address valid hold time
ALE to CSB
ALE to high Z state of bus
CSB to WRB
CSB to RDB
WR to data
WR to Dy asserted
RD to Rdy asserted
Rdyb to WRB
Rdyb to RDB
Data valid setup time
Data valid hold time
RdyB to CSB
master clock timing : cf specifications
Setup time according to the master clock
Setup time according to the master clock
Minimum
12
10
10
0
0
0
0
0
10
1/2 Tmclk
0
Maximum
900
50
15
60
60
Tmclk
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
10
ns
The timing are generally presented with the write signal, but as shown on the read diagram, they are also
valid for the read signal, so for example the Trdy2wr timing is the same as what can be Trdy2rd.
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