ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable
(tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface
control register.
Pin Description Utopia 2 (Receive Interface)
Name
RxClav
RxEnb*
RxClk
RxData
RxSOC
RxAddr
RxRef *
Type
Meaning
O Receive Cell available
I Receive Enable
I Receive Byte Clock
O Receive Data (8 bits)
O Receive Start Cell
I Receive Address (5 bits)
O Reference Clock
Usage
Remark
Signals to the ATM chip that
the STLC60135 has a cell
ready for transfer
Signals to the physical layer
that the ATM chip will sample
and accept data during next
clock cycle
Gives the timing signal for the
transfer, generated by ATM
layer chip.
ATM cell data, from physical
layer chip to ATM chip, byte
wide.
Identifies the cell boundary on
RxData
Use to select the port that will
be active or polled
8kHz clock transported over
the network
Remains active for the entire
cell transfer
RxData and RxSOC could be
tri-state when RxEnb* is
inactive (high)
Indicate to the ATM layer chip
that RxData contains the first
valid byte of a cell.
Note *Active low signal
Pin Description Utopia 2 (Transmit interface)
Name
TxClav
TxEnb*
TxClk
TxData
TxSOC
TxAddr
TxRef *
Type
Meaning
O Transmit Cell available
I Transmit Enable
I Transmit Byte Clock
I Transmit Data (8 bits)
I Transmit Start of Cell
I Transmit Address (5 bits)
I Reference Clock
Usage
Remark
Signals to the ATM chip that the Remains active for the entire
physical layer chip is ready to cell transfer
accept a cell
Signals to the physical layer
that TxData and TxSOC are
valid
Gives the timing signal for the
transfer, generated by ATM
layer chip.
ATM cell data, to physical layer
chip to ATM chip, byte wide.
Identifies the cell boundary on
TxData
Use to select the port that will
be active or polled
8kHz clock from the ATM layer
chip
Note *Active low signal
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