ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Pin Description
Name Type
Meaning
Usage
Remark
TxClav
TxEnb 1
TxClk
TxData
TxSOC
TxRef 1
O Transmit Cell
available
Signals to the ATM chip that the physical Remains active for the entire
layer chip is ready to accept a complete cell cell transfer
I Transmit Enable
Signals to the ST70235A that TxData and
TxSOC are valid
I Transmit Byte Clock Gives the timing signal for the transfer,
generated by ATM layer chip.
I Transmit Data (8bits) ATM cell data, from ATM layer chip to
ST70235A, byte wide. TxData [7] is the MSB.
I Transmit Start of Cell Identifies the cell boundary on TxData
TxData contains the first
valid byte of the cell.
I Reference Clock
8kHz clock from the ATM layer chip
Note 1. Active low signal
The ST70235A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted.
TxClk, RxClk, AC Electrical Characteristics
Symbol
F
Tc
Tj
Trf
L
Parameters
Clock frequency
Clock duty cycle
Clock peak to peak jitter
Clock rise fall time
Load
Minimum
1.5
40
Maximum
25
60
5
4
100
Unit
MHz
%
%
ns
pF
TxData, TxSOC, TxAddr, TxEnb, AC Electrical Characteristics
Symbol
T5
T6
L
Parameters
Input set-up time to TxClk
Hold time to TxClk
Load
Minimum Maximum
Unit
10
ns
1
ns
100
pF
Note: Tx data hold time is 1.2ns. All the UTOPIA hold time are guarantee by design.
RxData, RxSOC, RxClav, TxClav, AC Electrical Characteristics
Symbol
T7
T8
T9
T10
T11
T12
L
Parameters
Input set-up time to TxClk
Hold time to Tx Clk
Signal going low impedance to RxClk
Signal going High impedance to RxClk
Signal going low impedance to RxClk
Signal going High impedance to RxClk
Load
Minimum Maximum
Unit
10
ns
1
ns
10
ns
0
ns
1
ns
1
ns
100
pF
17/28
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