ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Figure 14 : Timing (Utopia 2 Receive Interface)
Polling:
Polling
Detection Selection
Polling
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RxClk
RxAddr 1F N-3 1F N+1 1F N-1 1F N 1F N+3 1F N-1 1F N-3 1F N-3 1F N+1 1F N+2
RxClav
N-3
N-3
N+1
N-3
N+1
N-1
N
N+3
N-1
RxEnb*
RxData P41 P42 P43 P44 P45 P46 P47 P48
XX
RxSOC
Cell transmission from:
PHY N
H1 H2 H3
PHY N-3
Pin Description
Name Type
Meaning
Usage
Remark
RxClav
RxEnb 1
RxClk
RxData
RxSOC
RxRef 1
O Receive Cell available Signals to the ATM chip that the ST70235A Remains active for the entire
has a cell ready for transfer
cell transfer
I Receive Enable
Signals to the ST70235A that the ATM chip
will sample and accept data during next
clock cycle
RxData and RxSOC could be
tri-state when RxEnb* is
inactive (high). Active low
signal
I Receive Byte Clock
Gives the timing signal for the transfer,
generated by ATM layer chip.
O Receive Data (8bits) ATM cell data, from ST70235A chip to ATM
chip, byte wide. Rx Data [7] is the MSB.
O Receive Start Cell
Identifies the cell boundary on RxData
Indicate to the ATM layer
chip that RxData contains
the first valid byte of a cell
O Reference Clock
8 kHz clock transported over the network Active low signal
Note 1. Active low signal
When RxEnb is asserted, the ST70235A reads data from its internal fifo and presents it on RxData and
RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on
the rising edge of RxSOC on the rising edge of RxClk.
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