ST72321BR9-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72321BR9-AUTO
STMicroelectronics
'ST72321BR9-AUTO' PDF : 247 Pages View PDF
Central processing unit (CPU)
ST72321Bxxx-Auto
5.3.5
Table 6. Arithmetic management bits (continued)
Bit Name
Function
Zero
1Z
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0C
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
Table 7. Interrupt management bits
Bit Name
Function
Interrupt Software Priority 1
5 I1
The combination of the I1 and I0 bits gives the current interrupt software priority.
3
I0
Interrupt Software Priority 0
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 8. Interrupt software priority selection
Interrupt software priority
Level
I1
I0
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Low
1
0
0
1
0
0
High
1
1
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See Chapter 7: Interrupts on page 55 for more details.
Stack pointer (SP) register
7
SP
15 14 13 12 11 10 9
0000000
Reset value: 01 FFh
876543210
1 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
RW RW RW RW RW RW RW RW
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