ST72321BR9-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72321BR9-AUTO
STMicroelectronics
'ST72321BR9-AUTO' PDF : 247 Pages View PDF
ST72321Bxxx-Auto
Supply, reset and clock management
Caution:
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of three phases as shown in Figure 12:
● Active phase depending on the RESET source
● 256 or 4096 CPU clock cycle delay (selected by option byte)
● RESET vector fetch
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see Section 21.1.1: Flash configuration on page 228).
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset block diagram
VDD
RESET
RON
Filter
INTERNAL
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
Figure 12. RESET sequence phases
ACTIVE PHASE
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
6.5.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 19.9: Control pin
characteristics on page 211 for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and
therefore the MCU can enter reset state even in Halt mode.
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