Supply, reset and clock management
6
Supply, reset and clock management
ST72321Bxxx-Auto
6.1
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 9.
For more details, refer to the dedicated parametric section.
6.2
Main features
● Optional PLL for multiplying the frequency by 2 (not to be used with internal RC
oscillator)
● Reset Sequence Manager (RSM)
● Multi-oscillator Clock Management (MO)
– 5 crystal/ceramic resonator oscillators
– 1 internal RC oscillator
● System Integrity Management (SI)
– Main supply low voltage detection (LVD)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply or the EVD pin
Figure 9. Clock, reset and supply block diagram
OSC2
OSC1
RESET
VSS
VDD
EVD
MULTI-
OSCILLATOR
(MO)
fOSC PLL
(option)
RESET SEQUENCE
MANAGER
(RSM)
fOSC2
MAIN CLOCK
CONTROLLER
fCPU
WITH REAL-TIME
CLOCK (MCC/RTC)
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
SICSR
AVD AVD AVD LVD
S IE F RF
0
0
0
WDG
RF
WATCHDOG
TIMER (WDG)
LOW VOLTAGE
DETECTOR
(LVD)
0
AUXILIARY VOLTAGE
DETECTOR
1
(AVD)
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