ST72321Bxxx-Auto
Figure 13. RESET sequences
VDD
VIT+(LVD)
VIT-(LVD)
RUN
LVD
RESET
Active Phase
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
Supply, reset and clock management
RUN
SHORT EXT.
RESET
Active
Phase
RUN
LONG EXT.
RESET
Active
Phase
RUN
WATCHDOG
RESET
Active
Phase
RUN
tw(RSTL)out
th(RSTL)in
tw(RSTL)out
th(RSTL)in
DELAY
tw(RSTL)out
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
6.6
6.6.1
System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT- reference value. This means that it secures the power-up as well as
the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
– VIT+ when VDD is rising
– VIT- when VDD is falling
The LVD function is illustrated in Figure 14.
The voltage threshold can be configured by option byte to be low, medium or high.
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