SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
15.8 Function description
The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface and controls the PB[4] and PB[5] pins.
This bit puts these two port B lines in the open drain configuration requested to use the USRT interface.
If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4]
and PBPullup[5] in RegPBPullup.
The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control
of USRT interface.
Figure 15-3 shows the unconditional clock stretching function which is enabled by setting UsrtEnWaitS0.
S0
Us rtW aitS 0
write Reg UsrtBufferS1
Figure 15-3: S0 Stretching (UsrtEnWaitS0=1)
When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is
then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1
register.
The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4
shows the conditional clock stretching function which is enabled by setting UsrtEnWaitCond1.
S1
S0
Us rtW aitS 0
write Reg UsrtBufferS1
© Semtech 2005
Figure 15-4: Conditional stretching (UsrtEnWaitCond1=1)
15-5
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