SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
When UsrtEnWaitCond1 is 1, the S0 signal will be stretched in its low state after its falling edge if the condition 1
has been detected before (UsrtCond1=1). UsrtWaitS0 is then set to 1, indicating that the S0 line is forced low.
One can release S0 by writing to the RegUsrtBufferS1 register.
Figure 15-5 shows the sampling function implemented by the UsrtBufferS1 bit. The bit UsrtBufferS1 in
RegUsrtBufferS1 is the value of S1 sampled on PB[4] at the last rising edge of S0. The bit UsrtEdgeS0 in
RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the
RegUsrtBufferS1 register. The bit therefor indicates that a new value is present in the RegUsrtBufferS1 which
was not yet read.
S1
S0
Us rtBu fferS 1
read Reg UsrtBufferS1
Us rt Edg eS 0
Figure 15-5: S1 sampling
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