XE8801A – SX8801R
pos. RegAcCfg2
rw
7:6
FIN[1:0]
rw
5:4
PGA2_GAIN[1:0] r w
3:0 PGA2_OFFSET[3:0] r w
reset
00 resetsystem
00 resetsystem
0000
resetsystem
description
Sampling frequency selection
PGA2 stage gain selection
PGA2 stage offset selection
Table 16-6: RegAcCfg2
pos.
7
6:0
RegAcCfg3
PGA1_GAIN
PGA3_GAIN[6:0]
rw reset
r w 0 resetsystem
r w 0000000
resetsystem
description
PGA1 stage gain selection
PGA3 stage gain selection
Table 16-7: RegAcCfg3
pos. RegAcCfg4
rw
7
reserved
r
6:0 PGA3_OFFSET[6:0] r w
reset
0
0000000
resetsystem
description
Unused
PGA3 stage offset selection
Table 16-8: RegAcCfg4
pos.
7
6
5:1
RegAcCfg5
BUSY
DEF
AMUX[4:0]
0
VMUX
rw reset
r
0 resetsystem
w r0 0
r w 00000
resetsystem
r w 0 resetsystem
description
Activity flag
Selects default configuration
Input channel configuration selector
Reference channel selector
Table 16-9: RegAcCfg5
16.4 ZoomingADC™ Description
Figure 16-2 gives a more detailed description of the acquisition chain.
16.4.1 Acquisition Chain
Figure 16-1 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure
16-1) manages all communications with the CoolRisc™ microcontroller.
Analog inputs can be selected among eight input channels, while reference input is selected between two differential
channels.
The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of a
combination of input and reference signals VIN and VREF, the input voltage is modulated and amplified through stages
1 to 3. Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide programmable
offset. Each amplifier can be bypassed if needed.
The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal
VIN,ADC into digital.
© Semtech 2005
16-4
www.semtech.com