T2080 View Datasheet(PDF) - Freescale Semiconductor
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Description
MFG CO.
'T2080' PDF : 29 Pages View PDF
Chip features
Table 3. DPAA terms and definitions (continued)
Term
Channel
Definition
Set of eight WQs with hardware provided prioritized access
Graphic representation
Dedicated
channel
Channel statically assigned to a particular end point, from which -
that end point can dequeue frames. End point may be a CPU,
FMan, PME, or SEC.
Pool channel A channel statically assigned to a group of end points, from which
any of the end points may dequeue frames.
4.10.2 Major DPAA components
The SoC's Datapath Acceleration Architecture, shown in the figure below, includes the following major components:
• Frame Manager (FMan)
• Queue Manager (QMan)
• Buffer Manager (BMan)
• RapidIO Message Manager (RMan 1.0)
• Security Engine (SEC 5.2)
• Pattern Matching Engine (PME 2.1)
• Decompression and Compression Engine (DCE 1.0)
The QMan and BMan are infrastructure components, which are used by both software and hardware for queuing and memory
allocation/deallocation. The Frame Managers and RMan are interfaces between the external world and the DPAA. These
components receive datagrams via Ethernet or Serial RapidIO and queue them to other DPAA entities, as well as dequeue
datagrams from other DPAA entities for transmission. The SEC, PME, and DCE are content accelerators that dequeue
processing requests (typically from software) and enqueue results to the configured next consumer. Each component is
described in more detail in the following sections.
T2080 Product Brief, Rev 0, 04/2014
12
Freescale Semiconductor, Inc.
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