T2080 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'T2080' PDF : 29 Pages View PDF
Chip features
• Common interface between software and all hardware
• Controls the prioritized queuing of data between multiple processor cores, network interfaces, and hardware
accelerators.
• Supports both dedicated and pool channels, allowing both push and pull models of multicore load spreading.
• Atomic access to common queues without software locking overhead
• Mechanisms to guarantee order preservation with atomicity and order restoration following parallel processing on
multiple CPUs
• Egress queuing for Ethernet interfaces
• Hierarchical (2-level) scheduling and dual-rate shaping
• Dual-rate shaping to meet service-level agreements (SLAs) parameters (1 Kbps...10 Gbps range, 1 Kbps
granularity across the entire range)
• Configurable combinations of strict priority and fair scheduling (weighted queuing) between the queues
• Algorithms for shaping and fair scheduling are based on bytes
• Queuing to cores and accelerators
• Two level queuing hierarchy with one or more Channels per Endpoint, eight work queues per Channel, and
numerous frame queues per work queue
• Priority and work conserving fair scheduling between the work queues and the frame queues
• Loss-less flow control for ingress network interfaces
• Congestion avoidance (RED/WRED) and congestion management with tail discard
4.10.2.3 Buffer Manager
The Buffer Manager (BMan) manages pools of buffers on behalf of software for both hardware (accelerators and network
interfaces) and software use.
The Buffer Manager offers the following features:
• Common interface for software and hardware
• Guarantees atomic access to shared buffer pools
• Supports 64 buffer pools
• Software, hardware buffer consumers can request different size buffers and buffers in different memory partitions
• Supports depletion thresholds with congestion notifications
• On-chip per pool buffer stockpile to minimize access to memory for buffer pool management
• LIFO (last in first out) buffer allocation policy
• Optimizes cache usage and allocation
• A released buffer is immediately used for receiving new data
4.10.2.4 Pattern Matching Engine (PME 2.1)
The PME 2.1 is Freescale's second generation of extended NFA style pattern matching engine. Unchanged from the first
generation QorIQ products, it supports ~10 Gbps data scanning.
Key benefits of a NFA pattern matching engine:
• No pattern "explosion" to support "wildcarding" or case-insensitivity
• Comparative compilations have shown 300,000 DFA pattern equivalents can be achieved with ~8000 extended
NFA patterns
• Pattern density much higher than DFA engines.
• Patterns can be stored in on-chip tables and main DDR memory
• Most work performed solely with on-chip tables (external memory access required only to confirm a match)
• No need for specialty memories; for example, QDR SRAM, RLDRAM, and so on.
• Fast compilation of pattern database, with fast incremental additions
• Pattern database can be updated without halting processing
• Only affected pattern records are downloaded
• DFA style engines can require minutes to hours to recompile and compress database
T2080 Product Brief, Rev 0, 04/2014
14
Freescale Semiconductor, Inc.
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