Chip features
4.12.1.2 Integrated Flash Controller
The SoC incorporates an Integrated Flash Controller similar to the one used in some previous generation QorIQ SoCs. The
IFC supports both NAND and NOR flash, as well as a general purpose memory mapped interface for connecting low speed
ASICs and FPGAs.
4.12.1.2.1 NAND Flash features
• x8/x16 NAND Flash interface
• Optional ECC generation/checking
• Flexible timing control to allow interfacing with proprietary NAND devices
• SLC and MLC Flash devices support with configurable page sizes of up to 8 KB
• Support advance NAND commands like cache, copy-back, and multiplane programming
• Boot chip-select (CS0) available after system reset, with boot block size of 8 KB, for execute-in-place boot loading
from NAND Flash
• Up to terabyte Flash devices supported
4.12.1.2.2 NOR Flash features
• Data bus width of 8/16
• Compatible with asynchronous NOR Flash
• Directly memory mapped
• Supports address data multiplexed (ADM) NOR device
• Flexible timing control allows interfacing with proprietary NOR devices
• Boot chip-select (CS0) available at system reset
4.12.1.2.3 General-purpose chip-select machine (GPCM)
The IFC's GPCM supports the following features:
• Normal GPCM
• Support for x8/16-bit device
• Compatible with general purpose addressable device, for example, SRAM and ROM
• External clock is supported with programmable division ratio (2, 3, 4, and so on, up to 16)
• Generic ASIC Interface
• Support for x8/16-bit device
• Address and Data are shared on I/O bus
• Following address and data sequences are supported on I/O bus:
• 16-bit I/O: AADD
• 8-bit I/O: AAAADDDD
4.13 Resource partitioning and QorIQ Trust Architecture
Consolidation of discrete CPUs into a single, multicore chip introduces many opportunities for unintended resource
contentions to arise, particularly when multiple, independent software entities reside on a single chip. A system may exhibit
erratic behavior if multiple software partitions cannot effectively partition resources. Device consolidation, combined with a
trend toward embedded systems becoming more open (or more likely to run third-party or open-source software on at least
one of the cores), creates opportunities for malicious code to enter a system.
This chip offers a new level of hardware partitioning support, allowing system developers to ensure software running on any
CPU only accesses the resources (memory, peripherals, and so on) that it is explicitly authorized to access. This section
provides an overview of the features implemented in the chip that help ensure that only trusted software executes on the
CPUs, and that the trusted software remains in control of the system with intended isolation.
T2080 Product Brief, Rev 0, 04/2014
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Freescale Semiconductor, Inc.