T2080 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'T2080' PDF : 29 Pages View PDF
• Transfer general data between two memory locations
Chip features
• Eight high-speed/high-bandwidth channels
• Basic DMA operation modes (direct, simple chaining)
• Extended DMA operation modes (advanced chaining and stride capability)
• Programmable bandwidth control between channels
• Three priority levels supported for source and destination transactions
• Can be activated using DREQ pin
• Optimized to work with the high speed interfaces
• Address translation and mapping unit (ATMU) which allows to define packet attributes as address/device/flow level/
transaction type. ATMU Bypass that allows the descriptor to specify the attributes.
4.12 Serial memory controllers
In addition to the parallel NAND and NOR flash supported by means of the IFC, the chip supports serial flash using eSPI and
SD/eSDHC/eMMC card and device interfaces. The SD/eSDHC/eMMC controller includes a DMA engine, allowing it to
move data from serial flash to external or internal memory following straightforward initiation by software.
Detailed features of the eSPI controller include the following:
• Supports SPI full-duplex or half-duplex single master mode with four independent chip-selects
• Supports RapidS™ full clock cycle operation, and Winbond dual output read
• Independent, programmable baud-rate generator
• Programmable clock phase and polarity
• Supports four different configurations per chip-select
Detailed features of the SD/eSDHC/eMMC controller include the following:
• Conforms to the SD Host Controller Standard Specification version 3.0
• Compatible with the MMC System Specification version 4.5
• Compatible with the SD Memory Card Physical Layer Specification version 3.01
• Compatible with the SD - SDIO Card Specification version 2.0
• Designed to work with eMMC devices as well as SD Memory, SDIO, and SD Combo cards and their variants
• Supports SD UHS-1 speed modes
4.12.1 PreBoot Loader and nonvolatile memory interfaces
The PreBoot Loader (PBL) operates on behalf of a large number of interfaces.
4.12.1.1 PreBoot Loader (PBL)
The PBL's functions include the following:
• Simplifies boot operations, replacing pin strapping resistors with configuration data loaded from nonvolatile memory
• Uses the configuration data to initialize other system logic and to copy data from low speed memory interfaces (I2C,
IFC, eSPI, SD/SDXC/eMMC) into fully initialized DDR or other access targets in the chip
• Releases CPU 0 from reset, allowing the boot processes to begin from fast system memory
T2080 Product Brief, Rev 0, 04/2014
Freescale Semiconductor, Inc.
19
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