T2080 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'T2080' PDF : 29 Pages View PDF
Chip features
SEC
QMan
PME
BMan
Frame Manager
Parse
and
Classify
DMA
1/2.5/10GE
Buffer
Buffer
DCE
RMan
1/2.5/10GE
1/2.5/10GE
1/2.5/10GE
1/2.5/10GE
1/2.5GE 1/2.5GE
1/2.5GE 1/2.5GE
Figure 4. T2080 DPAA Components
4.10.2.1 Frame Manager and network interfaces
The Frame Manager, or FMan, combines Ethernet MACs with packet parsing and classification logic to provide intelligent
distribution and queuing decisions for incoming traffic. The FMan supports PCD at 37.2 Mpps, supporting line rate 2x10G +
2x2.5G at minimum frame size.
These Ethernet combinations are supported:
• 12 Gbps Ethernet MACs are supported with Higig2 (four lanes at 3.75 GHz)
• 10 Gbps Ethernet MACs are supported with XAUI (four lanes at 3.125 GHz) or HiGig (four lanes at 3.125 GHz), XFI
or 10Gbase-KR (one lane at 10.3125 GHz).
• 1 Gbps Ethernet MACs are supported with SGMII (one lane at 1.25 GHz with 3.125 GHz option for 2.5 Gbps
Ethernet).
• Two MACs can be used with RGMII.
The Frame Manager's Ethernet functionality also supports the following:
• 1588v2 hardware timestamping mechanism in conjunction with IEEE Std. 802.3bf (Ethernet support for time
synchronization protocol)
• Energy Efficient Ethernet (IEEE Std. 802.3az)
• IEEE Std. 802.3bd (MAC control frame support for priority based flow control)
• IEEE Std. 802.1Qbb (Priority-based flow control) for up to eight queues/priorities
• IEEE Std. 802.1Qaz (Enhanced transmission selection) for three or more traffic classes
4.10.2.2 Queue Manager
The Queue Manager (QMan) is the primary infrastructure component in the DPAA, allowing for simplified sharing of
network interfaces and hardware accelerators by multiple CPU cores. It also provides a simple and consistent message and
data passing mechanism for dividing processing tasks amongst multiple vCPUs.
The Queue Manager offers the following features:
T2080 Product Brief, Rev 0, 04/2014
Freescale Semiconductor, Inc.
13
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