VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (1 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ Hi-Z
Da0 Da1 Da2 Da3 Db0 Db1 Dc0 Dc1 Dc2 Dc3
Dd0 Dd1
Activate
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Document : 1G5-0154
Rev.1
Page 45