VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (2 of 3)
Burs tLength=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
t
CK3
CS
RAS
CAS
WE
BS
A10
ADD
DQM
t
RCD
t
AC3
tRP
Hi-Z
DQ
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate
Command
Bank B
(Bank D)
Read
Command
Bank B
(Bank D)
Activate
Command
Bank A
Read Precharge
Command Command
Bank A
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D)
Read Precharge
Command Command
Bank B Bank A
(Bank D)
Document : 1G5-0154
Rev.1
Page 47