VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
t
CK2
CS
RAS
CAS
WE
BS
A10
ADD
DQM
t
RCD
t
DPL
tRP
t
DPL
DQ Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4
Activate
Write
Command Command
Bank A
Bank A
Activate
Precharge Active
Command
Bank B
Command Command
Bank A Bank A
(Bank D) Write
Command
Bank B
(Bank D)
Write
Command
Bank A
Precharge
Command
Bank B
(Bank D)
Document : 1G5-0154
Rev.1
Page 48