VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (2 of 2)
Burst Length=4, CAS Latency=3,4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
tCH tCL
CKE
tCKS
CS
tCMS
tCK3
tCMH
Begin Auto Precharge Begin Auto Precharge
Bank A
Bank B (Bank D)
tCKH
RAS
CAS
WE
BS
A10
ADD
tAS
tAH
DQM
DQ
tRCD
tRRD
tDAL
tRC
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
Activate
Command
Bank A
Write with Activate
Auto Precharge Command
Command Bank B
Bank A (Bank D)
Write with
Auto Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank A
tDS
tDH
tDPL
tRP
QAb0 QAb1 QAb2 QAb3
Write without
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Document : 1G5-0154
Rev.1
Page 31