VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Power Down Mode and Clock Mask
Burst Length=4, CAS Latency=2
CLK can be Stopped*
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK2
t
CKS
t
CKH
VALID
t
CKS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
Hi-Z
DQ
QAa0 QAa1
Activate
Command
Bank A
ACTIVE
STANDBY
Read
Command
Bank A
Power Down Power Down
Mode Entry Mode Exit
Clock Mask
Start
QAa2
t
HZ
QAa3
Clock Mask
End
Precharge
Command
Power Down
Mode Entry
Precharge
Standby
Power
Down
Mode
Exit Command
Document : 1G5-0154
Rev.1
Page 39