VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
8.4 Multibank Operation- Write with Auto Precharge
During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-pre-
charge scheduled time would not be changed.
Multibank Operation
T0
T1 T2 T3 T4 T5 T6
T7 T8
Burst lengh=8
T9 T10
CLK
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
WRITA A
Read B
DA0
DA1
WRITA A
Read B
DA0
DA1
Auto precharge bank A starts
DB0
DB1
DB2
DB3
DB4
DB5
Hi-Z
Auto precharge bank A starts
DB0
DB1
DB2
DB3
DB4
Hi-Z
Multibank Operation
T0 T1 T2
Burst lengh=8
T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
WRITA A
Write B
Auto precharge bank A starts
DA0
DA1
DB0 DB1 DB2 DB3 DB4 DB5 DB6
DB7
Hi-Z
Auto precharge bank A starts
WRITA A
Write B
DA0
DA1
DB0 DB1 DB2 DB3 DB4 DB5 DB6
DB7
Hi-Z
Document : 1G5-0154
Rev.1
Page 21
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