VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
9.3 Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before
the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
WRITE to READ Command Interval
CLK
Command
CAS latency=2
DQ
T0
T1
T2
1 cycle
WRITE A Read B
DA0
Hi-Z
Burst lengh=4
T3
T4
T5
T6
T7
T8
QB0
QB1
QB2
QB3
Command
CAS latency=3
DQ
Write A
Read B
Hi-Z
DA0
QB0
QB1
QB2
QB3
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data
conflict. The data bus must be Hi-Z using DQM before Write.
Document : 1G5-0154
Rev.1
Page 23
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