VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
10.BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command.
One is the burst stop command and the other is the precharge command.
10.1 BURST Stop Command
During a read burst. when the burst stop command is asserted, the burst read data are termi-
nated and the data bus goes to high-impedance after the CAS latency from the burst stop com-
mand.
During a write burst, when the burst stop command is asserted, any data provided at that cycle
will not be written. The burst write is effectively terminated and no further data can be written until a
new write command is asserted.
Burst Termination
CLK
Command
Burst lengh=X, CAS Intency=2,3
T0
T1
T2
T3
T4
T5
T6
T7
Read
BST
CAS latency=2
DQ
CAS latency=3
DQ
Hi-Z
Q0
Q1
Q2
Hi-Z
Q0
Q1
Q2
Remark BST: Burst stop command
Burst lengh=X, CAS latency=2,3
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Write
BST
CAS latency=2,3
DQ
Q0
Q0
Q1
Q2
Hi-Z_
Remark BST: Burst command
Document : 1G5-0154
Rev.1
Page 25
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