VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
9.Read/Write Command Interval
9.1 Read to Read command interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency,
even if the previous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Read A
Read B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the
new burst will begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Write A
Write B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
Document : 1G5-0154
Rev.1
Page 22
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