VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
10.2.2 Precharge Termination in WRITE Cycle
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
During WRITE cycle, the burst write operation is terminated by a precharge com-
mand. When the precharge command is asserted, the burst write operation is termi-
nated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The
DQM must be high to mask invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be
correctly stored. However, invalid data may be written at the same clock as the pre-
charge command. To prevent this from happening, DQM must be high at the same
clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
CAS latency = 2
DQM
DQ
command
CAS latency = 3
DQM
DQ
Write
PRE
ACT
D0
D1
D2
Write
D3
D4
tRP
PRE
Hi - Z
ACT
D0
D1
D2
D3
D4
Hi - Z
tRP
Document : 1G5-0154
Rev.1
Page 27
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