VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
Hi-Z
DQ
DAa0
DAa1
DAa2
DAa3
Activate
Command
Bank A
Clock
Suspended
1 Cycle
Write
Command
Bank A
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Document : 1G5-0154
Rev.1
Page 38