XRT7302IQ80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IQ80' PDF : 77 Pages View PDF
XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
áç
REV. 1.1.0
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single Rail or Dual Rail data from
Terminal Equipment, and generates a bipolar signal
• Integrated Pulse Shaping Circuit
• Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
• Contains "Transmit Clock Duty Cycle Correction"
Circuit on-chip
• Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
• Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
• Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
• Transmitter can be turned off in order to support
"redundancy designs"
PIN OUT OF THE XRT7302
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization
(Optional) and Timing Recovery
• Declares and Clears the LOS alarm per ITU-T
G.775 requirements (E3 and DS3 applications)
• Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 (for E3 Applications)
• Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE (for DS3 Applications)
• Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
• Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
• Recovered Data can be automatically muted while
the LOS Condition is declared
• Outputs either Single Rail or Dual Rail data to the
Terminal Equipment
• Receiver can be powered down in order to con-
serve power in "redundancy designs"
TxLEV1
1
TAOS1
2
VDD
3
DMO1
4
GND
5
GND
6
VDD
7
Host/(HW)
8
RxClk1
9
RNEG1
10
RPOS1
11
GND
12
RLOS1
13
LCV1
14
RLOL1
15
EXClk1
16
CS/(ENDECDIS)
17
SClk/(RxOff2)
18
SDI/(RxOff1)
19
SDO/(E3_Ch1)
20
80 Lead TQFP
60
TxLEV2
59
TAOS2
58
VDDD
57
DMO2
56
GNDA
55
GNDA
54
VDDD
53
LOSMUTEN
52
RxClk2
51
RNEG2
50
RPOS2
49
GNDD
48
RLOS2
47
LCV2
46
RLOL2
45
EXClk2
44
VDD
43
GND
42
REGR/(RxClkINV)
41
STS-1/DS3_Ch2
2
Share Link: 
