XRT7302IQ80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IQ80' PDF : 77 Pages View PDF
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
LIST OF FIGURES
REV. 1.1.0
Figure 1.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel shown) ...... 23
Figure 2.Timing Diagram of the Transmit Terminal Input Interface ................................................................ 23
Figure 3.Timing Diagram of the Receive Terminal Output Interface .............................................................. 24
Figure 4.Microprocessor Serial Interface Data Structure ............................................................................... 24
Figure 5.Timing Diagram for the Microprocessor Serial Interface .................................................................. 25
Figure 6.Functional Block Diagram of the XRT7302 Device .......................................................................... 27
Figure 7. Illustration of the typical interface for the Transmission of Data in a Dual Rail Format, from the "Trans-
mitting" Terminal Equipment to the "Transmit Section" of a channel within the XRT7302 Device ................. 30
Figure 8.Illustration on how the XRT7302 Device Samples the data on the TPData and TNData input pins 30
Figure 9.Illustration of the Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is
Accepting Single-Rail Data from the Terminal Equipment ............................................................................. 31
Figure 10.An Example of B3ZS Encoding ...................................................................................................... 32
Figure 11.An Example of HDB3 Encoding ..................................................................................................... 33
Figure 12.The "Bellcore GR-499-CORE" Transmit Output Pulse Template for DS3 Applications ................. 34
Figure 13.The "Bellcore GR-253-CORE" Transmit Output Pulse Template for SONET STS-1 Applications . 35
Figure 14.Recommended Schematic for Interfacing the Transmit Section of the XRT7302 Device to the Line .
37
Figure 15.Recommended Schematic for Interfacing the Receive Section of the XRT7302 Device to the Line
(Transformer-Coupling) .................................................................................................................................. 38
Figure 16.Recommended Schematic for Interfacing the Receive Section of the XRT7302 device to the Line (Ca-
pacitive-Coupling) - (typical channel shown) .................................................................................................. 39
Figure 17.Illustration of the Typical Application for the System Installer ........................................................ 40
Figure 18.An Example of B3ZS Decoding ...................................................................................................... 42
Figure 19.An Example of HDB3 Decoding ..................................................................................................... 43
Figure 20.Illustration of the Signal Levels that the XRT7302 device will declare and clear LOS ................... 44
Figure 21.The Behavior the LOS Output Indicator, in response to the Loss of Signal, and the Restoration of Sig-
nal ................................................................................................................................................................... 45
Figure 22.Illustration of the typical interface for the Transmission of Data in a Dual-Rail Format, from the "Re-
ceive Section" of the XRT7302 device" to the Receiving Terminal Equipment .............................................. 49
Figure 23.Illustration on how the XRT7302 Device outputs data on the RPOS and RNEG output pins ........ 49
Figure 24.Illustration of the Behavior of the RPOS, RNEG, and RxClk(n) signals, when RxClk(n) is inverted ...
50
Figure 25.Illustration of the typical interface for the Transmission of Data in a "Single-Rail Format", from the "Re-
ceive Section of the XRT7302 device" to the Receiving Terminal Equipment ............................................... 51
Figure 26.Illustration of the behavior of the RPOS and RxClk output signals, while the XRT7302 device is trans-
mitting "Single-Rail" data to the Receiving Terminal Equipment .................................................................... 51
Figure 27.Illustration of a Typical Channel(n) (within the XRT7302 Device) operating in the Analog Local Loop-
back Mode ...................................................................................................................................................... 53
Figure 28.Illustration of the "Digital Local Loop-back" path in a Typical Channel(n) (of the XRT7302 Device) ..
55
Figure 29.Illustration of the "Remote Loop-back" path, within a Typical Channel(n) (of the XRT7302 Device) ..
56
Figure 30.Illustration of a Typical Channel of the XRT7302 employing the Transmit Drive Monitor Features 58
Figure 31.Microprocessor Serial Interface Data Structure ............................................................................. 69
Figure 32.Timing Diagram for the Microprocessor Serial Interface ................................................................ 69
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