XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
RECEIVE SERIAL DATA OUTPUT
(Framer Channel Number indicated by _n)
REV. 1.0.1
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
RxTSClk_0
RxTSClk_1
RxTSClk_2
RxTSClk_3
RxTSClk_4
RxTSClk_5
RxTSClk_6
RxTSClk_7
C4
D11
D18
A25
V24
AD25
AF15
AC9
O Receive Channel Clock Output Signal—Framer_n:
This pin indicates the boundary of each time slot of an inbound DS1/E1 frame.
DS1 Mode:
Each of these output pins are a 192kHz clock output which pulses "High" when-
ever the Receive Payload Data Output Interface block outputs the LSB of each
of the 24 time slots (within the inbound DS1 data stream) on the RxSer_n pin.
The Terminal Equipment should use this clock signal to sample the RxTSb0_n
through RxTSb4_n output signals, and identify the time-slot being processed via
the "Receive Section" of each Framer_n.
If RxTSb1_n pin is configured as RxFrTD_n to output fractional DS1 payload
data from Framer_n, the RxTSClk_n pin can be configured to function as one of
the following:
The pin will output gaped fractional DS1 clock that can be used by terminal
equipment to clock out fractional DS1 payload data at rising edge of the clock.
Otherwise, this pin will be a clock enable signal to Receive fractional DS1 Out-
put (RxFrTD_n) if Framer_n is configured accordingly. In this mode, fractional
DS1 payload data is clocked into the terminal equipment using un-gapped
RxSerClk_n.
E1 Mode:
Each of these output pins are a 256kHz clock output which pulses "High" when-
ever the Receive Payload Data Output Interface block outputs the LSB of each
of the 32 time slots (within the inbound E1 data stream) on the RxSer_n pin. The
Terminal Equipment should use this clock signal to sample the RxTSb0_n
through RxTSb4_n output signals, and identify the time-slot being processed via
the "Receive Section" of each Framer_n.
If RxTSb1_n pin is configured as RxFrTD_n to output fractional E1 payload data
from Framer_n, the RxTSClk_n pin can be configured to function as one of the
following: The pin will output gaped fractional E1 clock that can be used by ter-
minal equipment to clock out fractional E1 payload data at rising edge of the
clock.
Otherwise, this pin will be a clock enable signal to Receive fractional E1 Output
(RxFrTD_n) if Framer_n is configured accordingly. In this mode, fractional E1
payload data is clocked into the terminal equipment using un-gaped
RxSerClk_n.
RxLOS_0
RxLOS_1
RxLOS_2
RxLOS_3
RxLOS_4
RxLOS_5
RxLOS_6
RxLOS_7
D2
O Receive Loss of Signal Output Indicator—Framer_n:
H4
This output pin will toggle “High” (declare LOS) if the Receive block associated
J1
with Framer_n determines that neither the RxPOS_n or the RxNEG_n inputs
L4
have received a High level pulse in the last 32 bit periods.
U1
This output pin will toggle “Low” if the Receive block, associated with Framer_n,
Y1
detects a string of 32 consecutive bits, that does not contain a string of 4 con-
AA3
secutive “0’s”.
AB4
NOTE: This output pin will also toggle "High" if the LOS_0 input pin is asserted
(e.g., toggled “High” by the LIU LOS output pin).
RxCASMSync_0
RxCASMSync_1
RxCASMSync_2
RxCASMSync_3
RxCASMSync_4
RxCASMSync_5
RxCASMSync_6
RxCASMSync_7
A4
A11
B18
D24
Y24
AD23
AD12
AC10
O Receive “CAS Multiframe” Sync Output Signal--Framer_n:
This E1-only signal pulses "High" for one period of RxSerClk_n whenever the
Receive E1 Output Interface of Framer_n outputs the first bit, within a given
"CAS Multiframe".
NOTE: This output pin is inactive if Common Channel Signaling is enabled.
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