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XRT84L38 View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
XRT84L38
Exar
Exar Corporation Exar
'XRT84L38' PDF : 453 Pages View PDF
REV. 1.0.1
JTAG
(Framer Channel Number indicated by _n)
XRT84L38
OCTAL T1/E1/J1 FRAMER
SIGNAL NAME
TDI
TDO
TRST
Test Mode
PIN #
B1
D3
C3
P3
TYPE
I
DESCRIPTION
Test Data In: Boundary Scan Test data input
Note: This input pin should be pulled “Low” for normal operation
O Test Data Out: Boundary Scan Test data output
I JTAG Test Reset Input
I Factory Test Mode Pin
Note: User should tie this pin to ground
MICROPROCESSOR INTERFACE
(Framer Channel Number indicated by _n)
SIGNAL NAME
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Req0
PIN #
R24
R25
N26
N25
L24
K25
K24
J24
T26
TYPE
DESCRIPTION
I/O Bidirectional Microprocessor Data Bus Bit 0--LSB
Bidirectional Microprocessor Data Bus Bit 1
Bidirectional Microprocessor Data Bus Bit 2
Bidirectional Microprocessor Data Bus Bit 3
Bidirectional Microprocessor Data Bus Bit 4
Bidirectional Microprocessor Data Bus Bit 5
Bidirectional Microprocessor Data Bus Bit 6
Bidirectional Microprocessor Data Bus Bit 7--MSB
O DMA Cycle Request Output—DMA Controller 0 (Write):
The Framer asserts this output pin (toggles it "Low") when at least one of the
Transmit HDLC buffers are empty and can receive one more HDLC message.
The Framer negates this output pin (toggles it “High”) when the HDLC buffer
can no longer receive another HDLC message.
Req1
INT
µPClk
U23
DMA Cycle Request Output—DMA Controller 1 (Read):
The Framer asserts this output pin (toggles it "Low") when one of the Receive
HDLC buffer contains a complete HDLC message that needs to be read by the
µC/µP.
The Framer negates this output pin (toggles it High) when the Receive HDLC
buffers are depleted.
M24
O Interrupt Request Output:
The Framer will assert this active "Low" output (toggles it "Low"), to the local µP,
anytime it requires interrupt service.
R23
I Microprocessor Clock Input:
This clock signal is the Microprocessor Interface System clock. This clock signal
is used for synchronous/burst/DMA data transfer. The maximum frequency of
this clock signal is 33MHz.
27
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