XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
REV. 1.0.1
MICROPROCESSOR INTERFACE
(Framer Channel Number indicated by _n)
XRT84L38
OCTAL T1/E1/J1 FRAMER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
WR
G26
I Microprocessor Interface—Write Strobe Input
"Low" : Indicates current bus cycle is a write cycle: Intel 51, 188, MIPS350x
"High" : Indicates present bus cycle is a write cycle: Intel x86, i960
"Low" : Indicates current bus cycle is a read cycle: Intel x86, i960
"High" : Indicates present bus cycle is a read cycle: Motorola, Power PC 403
"Low" : Also used as write strobe in DMA transfer
ACK0
U26
I DMA Cycle Acknowledge Input—DMA Controller 0 (Write):
The external DMA Controller will assert this input pin “Low” when the following
two conditions are met:
a. After the DMA Controller, within the Framer has asserted (toggled “Low”), the
Req_0 output signal.
b. When the external DMA Controller is ready to transfer data from external
memory to the selected Transmit HDLC buffer.
At this point, the DMA transfer between the external memory and the selected
Transmit HDLC buffer may begin.
After completion of the DMA cycle, the external DMA Controller will negate this
input pin after the DMA Controller within the Framer has negated the Req_0 out-
put pin. The external DMA Controller must do this in order to acknowledge the
end of the DMA cycle.
ACK1
Blast
Reset
T23
I DMA Cycle Acknowledge Input—DMA Controller 1 (Read):
The external DMA Controller asserts this input pin “Low” when the following two
conditions are met:
a. After the DMA Controller, within the Framer has asserted (toggled "Low"), the
Req_1 output signal.
b. When the external DMA Controller is ready to transfer data from the selected
Receive HDLC buffer to external memory.
At this point, the DMA transfer between the selected Receive HDLC buffer and
the external memory may begin.
After completion of the DMA cycle, the external DMA Controller will negate this
input pin after the DMA Controller within the Framer has negated the Req_1 out-
put pin. The external DMA Controller will do this in order to acknowledge the
end of the DMA cycle.
L25
I Last Cycle of Burst Indicator Input:
The Microprocessor asserts this pin “Low”when it is performing its last read or
write cycle, within a burst operation.
R3
I Reset Input: Active "Low"
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