XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
LIU CONTROL
(Framer Channel Number indicated by _n)
REV. 1.0.1
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
GPO3
CS0
M1
O General Purpose Output pin/Chip Select Output pin:
The exact role of this output pin depends upon whether the LIU Controller block
is operating in the Hardware or HOST Mode.
Hardware Mode: GPO3
This pin is a general purpose output pin that is controlled by the contents of bit-
field 3, within the Line Control Register (Address = 0x00, 0x02).
HOST Mode: CS0
This pin is a chip select output pin that is asserted (toggles “Low”) following a
write operation to the LIU Access Register 1, associated with framer 0,1, 2 and
3. This output pin is intended to be tied to the chip select input of an LIU (or
other peripheral device) that is configurable via a Microprocessor Serial Inter-
face. Once the HOST Mode serial port has completed its read or write opera-
tion, then it will negate (toggle "High") this output pin.
GPO2
SClk0
GPO1
SDI0
N2
O General Purpose Output/Serial Clock Output:
The exact role of this output pin depends upon whether the LIU Controller block
is operating in the Hardware or HOST Mode.
Hardware Mode: GPO2
This pin is a general purpose output pin that is controlled by the contents of bit-
field 2, within the Line Control Register (Address = 00h, 02h).
HOST Mode: SClk0
This pin functions as the Serial Clock output signal (SCLK), when the LIU Con-
troller Block is configured to operate in the HOST Mode.
N3
O General Purpose Output pin/Serial Data In Output pin:
The exact role of this output pin depends upon whether the LIU Controller block
is operating in the Hardware or HOST Mode.
Hardware Mode: GPO1
This pin is a general purpose output pin that is controlled by the contents of bit
field 1, within the Line Control Register (Address = 00h, 02h)
HOST Mode: SDI
This pin functions as the Serial Data Input (SDI) output pin (to the Microproces-
sor Serial Interface).
GPO0
SDO0
N1
I or O General Purpose Output pin/Serial Data Out Input pin:
The exact role of this pin depends upon whether the LIU Controller block is
operating in the Hardware or HOST Mode.
Hardware Mode: GPO0
This pin is a general purpose output pin that is controlled by the contents of bit-
field 0, within the Line Control Register (Address = 00h, 02h).
HOST Mode: SDO0
This Input pin functions as the Serial Data Output (SDO) input pin (into the LIU
Controller Block).
JTAG
(Framer Channel Number indicated by _n)
SIGNAL NAME
TCK
TMS
PIN #
A1
C2
TYPE
I
I
DESCRIPTION
Test clock: Boundary Scan clock input.
Note: This input pin should be pulled “Low” for normal operation
Test Mode Select: Boundary Scan Mode Select input.
Note: This input pin should be pulled “Low” for normal operation
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