XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
Line Control Register (LCR) (Indirect Address = 0xn0H, 0x02H)
BIT 7
BIT 6
BIT 5
BIT 4
BIT3
BIT 2
GPIO
GPIO
GPIO
GPIO
Direction
Direction
Direction
Direction
Control Bit 3 Control Bit 2 Control Bit 1 Control Bit 0
GPIO Bit 3
GPIO Bit 2
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
0
BIT 1
GPIO Bit 1
R/W
0
BIT 0
GPIO Bit 0
R/W
0
BIT NUMBER
BIT NAME
7-4
GPIO Direction Control
3-0
GPIO
BIT TYPE
BIT DESCRIPTION
R/W GPIO Direction Control:
These READ/WRITE bit-fields control directions of the four on-
chip General Purpose Input/Output pins.
When these bits are set to zero:
The corresponding GPIO pins are configured as inputs. The user
can now apply signals to the GPIO pins by writing to the corre-
sponding GPIO bit-fields.
When these bits are set to one:
The corresponding GPIO pins are configured as outputs. The
user can read the output values by reading the corresponding
GPIO bit-fields.
R/W GPIO:
These READ/WRITE bit-fields contain values of the four on-chip
General Purpose Input/Output pins.
When the corresponding GPIO Direction Control bit-fields are
set to zero, the GPIO pins are configured as inputs. The GPIO
bit-fields contain values to be present on the GPIO pins. For
example, if the user wants to pull the pin GPIO_0 HIGH, he/she
can write zero into the GPIO Direction Control Bit 0; then write
one into the GPIO Bit 0.
When the corresponding GPIO Direction Control bit-fields are
set to one, the GPIO pins are configured as outputs. The GPIO
bit-fields contain values currently present on the GPIO pins.
LIU Access Register 1 (LAR1) (Indirect Address = 0xn0H, 0x03H)
BIT 7
BIT 6
BIT 5
BIT 4
BIT3
BIT 2
LAR1 Bit 7 LAR1 Bit 6 LAR1 Bit 5 LAR1 Bit 4 LAR1 Bit 3 LAR1 Bit 2
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
BIT 1
LAR1 Bit 1
R/W
0
BIT 0
LAR1 Bit 0
R/W
0
BIT NUMBER
BIT NAME
7-0
LAR1
BIT TYPE
R/W
BIT DESCRIPTION
64