XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
BIT NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
3-2
CRC-4 Selection bit
R/W CRC-4 Selection:
These Read/Write bit fields allow the user to enable searching of
CRC-4 Multi-frame alignment and determine what criteria are
used for locking the CRC-4 Multi-frame alignment pattern.
When these bit s are set to 00:
Searching of CRC-4 Multi-frame alignment is disabled. The
XRT84L38 framer will not search for CRC-4 Multi-frame align-
ment and thus will not declare CRC-4 Multi-frame synchroniza-
tion. No Receive CRC-4 Multi-frame Synchronization
(RxCRCMsync_n) pulse will be generated by the framer.
When these bit s are set to 01:
Searching of CRC-4 Multi-frame alignment is enabled. The
XRT84L38 will search for and declare CRC-4 Multi-frame syn-
chronization if:
At least one valid CRC-4 Multi-frame alignment signal is
observed within 8 ms.
When these bit s are set to 10:
Searching of CRC-4 Multi-frame alignment is enabled. The
XRT84L38 will search for and declare CRC-4 Multi-frame syn-
chronization if:
At least two valid CRC-4 Multi-frame alignment signals are
observed within 8 ms.
The time separating two CRC-4 Multi-frame alignment signals is
multiple of 2 ms.
When these bit s are set to 11:
Searching of CRC-4 Multi-frame alignment is enabled. The
XRT84L38 will search for and declare CRC-4 Multi-frame syn-
chronization if:
At least three valid CRC-4 Multi-frame alignment signals are
observed within 8 ms.
The time separating two CRC-4 Multi-frame alignment signals is
multiple of 2 ms.
1
FAS Alignment Frame
R/W FAS Alignment Frame Check Sequence Enable:
Check Sequence Enable
This READ/WRITE bit-field enables frame check sequence in
FAS alignment process. The frame check sequence consists of
verifying correct frame alignment for an additional two frames.
When this bit is set to 0:
The frame check sequence is disabled in FAS alignment pro-
cess.
When this bit is set to 1:
The frame check sequence is enabled in FAS alignment pro-
cess.
70