28F256L18 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'28F256L18' PDF : 106 Pages View PDF
Numonyx™ StrataFlash® Wireless Memory (L18)
Figure 14: Synchronous Single-Word Array or Non-array Read Timing
Latency Count
CLK [C]
R301
R306
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
R105
R101
R104
R303
R102
R106
R7
R15
Data [D/Q]
R2
R3
R4
R307
R304
R8
R9
R312 R17
R305
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Figure 15: Continuous Burst Read, showing an Output Delay Timing
CLK [C]
Address [A]
ADV# [V]
CE# [E]
R301
R302
R306
R2
R101
R106
R105
R303
R102
R3
R304
R304
R304
OE# [G]
WAIT [T]
Data [D/Q]
R15
R4
R7
R307
R304
R312
R305
R305
R305
R305
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR[10] = 0 Wait asserted low).
2.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned.
November 2007
251902-12
Datasheet
33
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