Numonyx™ StrataFlash® Wireless Memory (L18)
Figure 20: Write to Asynchronous Read Timing
Address [A]
ADV# [V]
W2
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
W5
W3
W8
W6
W18
W14
Data [D/Q]
W1
RST# [P]
W4
W7
D
R1
R10
R15
R4
R2
R3
R17
R8
R9
Q
Figure 21: Synchronous Read to Write Timing
CLK [C ]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
W E#
WAIT [T]
Data [D/Q]
R 30 1
R 302
R 30 6
Lat ency C ount
R2
R 10 1
R 10 5
R 10 2
R 106
R 30 3
R3
R4
R 16
R7
R 307
R 304
W5
W 18
R 104
R 11
R 13
W6
R8
R 312
W22
W2
W 21
W8
W3
W21
W22
W15
W9
R 305
Q
W7
D
D
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait asserted low). Clock is
ignored during write operation.
November 2007
251902-12
Datasheet
37