28F256L18 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'28F256L18' PDF : 106 Pages View PDF
Numonyx™ StrataFlash® Wireless Memory (L18)
8.0
8.1
8.2
Power and Reset Specifications
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected
together; If VCCQ and/or VPP are not connected to the VCC supply, then VCC should
attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before
supply voltage equals VCCMIN.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
Reset
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active-low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
System designers should guard against spurious writes when VCC voltages are above
VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting
either signal inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because
alteration of memory contents can only occur after successful completion of a two-step
command sequence (see Section 9.2, “Device Commands” on page 44).
Table 18: Reset Specifications
Nbr. Symbol
Parameter
Min
Max
Unit
Notes
P1 tPLPH
P2 tPLRH
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
100
-
-
25
-
25
ns
1,2,3,4
1,3,4,7
µs
1,3,4,7
P3 tVCCPH
VCC Power valid to RST# deassertion (high)
60
-
1,4,5,6
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if tPLPH is < tPLPHmin, but this is not guaranteed.
3.
Not applicable if RST# is tied to Vcc.
4.
Sampled, but not 100% tested.
5.
If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCC min.
6.
If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥
VCC(min).
7.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Datasheet
40
November 2007
251902-12
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