28F256L18 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'28F256L18' PDF : 106 Pages View PDF
Numonyx™ StrataFlash® Wireless Memory (L18)
Figure 16: Synchronous Burst-Mode Four-Word Read Timing
CLK [C]
Address [A]
ADV# [V]
CE# [E]
R302
R301 R306
R101
A
R105
R102
R106
R303
Latency Count
R2
R3
OE# [G]
WAIT [T]
Data [D/Q]
R15
R4
R7
R307
R304
R304
R305
Q0
Q1
R8
R9
R17
R10
Q2
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR[10] = 0 Wait asserted low).
Figure 17: Burst Suspend Timing
R304
R305
CLK
R305
Address [A]
ADV#
CE# [E]
OE# [G]
WAIT [T]
R2
R101
R105
R106
R3
R4
R15
R1
R9
R4
R17
R15
R312
WE# [W]
DATA [D/Q]
R7
R6
R304
Q0
Q1
R304
Q1
Q2
Notes:
1.
CLK can be stopped in either high or low state.
2.
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR[10] = 0 Wait asserted low).
Datasheet
34
November 2007
251902-12
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