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ADSP-21477 View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADSP-21477
ADI
Analog Devices ADI
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Table 35. Serial Ports—Internal Clock
88-Lead LFCSP Package
Parameter
Min
Max
Timing Requirements
tSFSI1 Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit 13
or Receive Mode)
tHFSI1 Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit 2.5
or Receive Mode)
tSDRI1 Receive Data Setup Before SCLK
13
tHDRI1 Receive Data Hold After SCLK
2.5
Switching Characteristics
tDFSI2 Frame Sync Delay After SCLK (Internally Generated
5
Frame Sync in Transmit Mode)
tHOFSI2 Frame Sync Hold After SCLK (Internally Generated –1.0
Frame Sync in Transmit Mode)
tDFSIR2 Frame Sync Delay After SCLK (Internally Generated
10.7
Frame Sync in Receive Mode)
tHOFSIR2 Frame Sync Hold After SCLK (Internally Generated –1.0
Frame Sync in Receive Mode)
tDDTI2
tHDTI2
tSCKLIW
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
–1.0
2 × tPCLK – 1.5
4
2 × tPCLK + 1.5
1 Referenced to the sample edge.
2 Referenced to drive edge.
All Other Packages
Min
Max
10.5
2.5
10.5
2.5
5
–1.0
10.7
–1.0
–1.0
2 × tPCLK – 1.5
4
2 × tPCLK + 1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. C | Page 42 of 76 | July 2013
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