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ADSP-21477 View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADSP-21477
ADI
Analog Devices ADI
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 39. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 39. Input Data Port (IDP)
88-Lead LFCSP Package
All Other Packages
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge 4.5
3.8
ns
tSIHFS1
Frame Sync Hold After Serial Clock Rising Edge 3
2.5
ns
tSISD1
Data Setup Before Serial Clock Rising Edge
4
2.5
ns
tSIHD1
Data Hold After Serial Clock Rising Edge
3
2.5
ns
tIDPCLKW
Clock Width
(tPCLK × 4) ÷ 2 – 1
(tPCLK × 4) ÷ 2 – 1
ns
tIDPCLK
Clock Period
tPCLK × 4
tPCLK × 4
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s input
can be either CLKIN or any of the DAI pins.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
SAMPLE EDGE
tIPDCLKW
tIPDCLK
tSISFS
tSIHFS
tSISD
tSIHD
Figure 26. IDP Master Timing
Rev. C | Page 47 of 76 | July 2013
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