ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Table 36. Serial Ports—External Late Frame Sync
88-Lead LFCSP Package All Other Packages
Parameter
Min
Max
Min
Max
Switching Characteristics
tDDTLFSE1
Data Delay from Late External Transmit Frame Sync or
2 × tPCLK
13.5
External Receive Frame Sync with MCE = 1, MFD = 0
tDDTENFS1
Data Enable for MCE = 1, MFD = 0
0.5
0.5
1 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.
Unit
ns
ns
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
SAMPLE
DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tHDTE/I
1ST BIT
tDDTE/I
tDDTLFSE
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE
LATE EXTERNAL TRANSMIT FS
SAMPLE
DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tHDTE/I
1ST BIT
tDDTE/I
tDDTLFSE
Figure 23. External Late Frame Sync1
1 This figure reflects changes made to support left-justified mode.
2ND BIT
2ND BIT
Rev. C | Page 44 of 76 | July 2013
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