ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 40. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-214xx SHARC Processor Hardware
Reference. Note that the 20 bits of external PDAP data can be
provided through the ADDR23–0 pins or over the DAI pins.
Table 40. Parallel Data Acquisition Port (PDAP)
88-Lead LFCSP Package All Other Packages
Parameter
Min
Max Min
Max Unit
Timing Requirements
tSPHOLD1
tHPHOLD1
tPDSD1
tPDHD1
PDAP_HOLD Setup Before PDAP_CLK Sample Edge
4
PDAP_HOLD Hold After PDAP_CLK Sample Edge
4
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 5
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 4
2.5
ns
2.5
ns
3.85
ns
2.5
ns
tPDCLKW
Clock Width
(tPCLK × 4) ÷ 2 – 3
(tPCLK × 4) ÷ 2 – 3
ns
tPDCLK
Clock Period
tPCLK × 4
tPCLK × 4
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK
2 × tPCLK + 3
2 × tPCLK + 3
ns
Capture Edge for a Word
tPDSTRB
PDAP Strobe Pulse Width
2 × tPCLK – 1.5
2 × tPCLK – 1.5
ns
1 Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
DAI_P20–1
(PDAP_CLK)
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
DAI_P20–1
(PDAP_STROBE)
SAMPLE EDGE
tPDCLKW
tPDCLK
tSPHOLD
tHPHOLD
tPDSD
tPDHD
tPDHLDD
tPDSTRB
Figure 27. PDAP Timing
Rev. C | Page 48 of 76 | July 2013
Share Link: 
