ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Sample Rate Converter—Serial Output Port
For the serial output port, the frame sync is an input, and it
should meet setup and hold times with regard to the serial clock
on the output port. The serial data output has a hold time and
delay specification with regard to serial clock. Note that serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
Table 42. ASRC, Serial Output Port
88-Lead LFCSP Package
All Other Packages
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSRCSFS1
Frame Sync Setup Before Serial Clock Rising Edge
tSRCHFS1
Frame Sync Hold After Serial Clock Rising Edge
tSRCCLKW
Clock Width
tSRCCLK
Clock Period
Switching Characteristics
4
5.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
4
ns
5.5
ns
(tPCLK × 4) ÷ 2 – 1
ns
tPCLK × 4
ns
tSRCTDD1
tSRCTDH1
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge 1
2 × tPCLK
1
13
ns
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
be either CLKIN or any of the DAI pins.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
SAMPLE EDGE
tSRCCLKW
tSRCCLK
tSRCSFS
tSRCHFS
tSRCTDD
tSRCTDH
Figure 29. ASRC Serial Output Port Timing
Rev. C | Page 50 of 76 | July 2013
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